EMCBC=BURST_ENABLED_, EMCSC=STATIC_MEMORY_ADDRES, OSCRS=THE_FREQUENCY_RANGE_, OSCSTAT=THE_MAIN_OSCILLATOR_, EMCRD=BOTH_EMC_RESETS_ARE_, OSCEN=THE_MAIN_OSCILLATOR_, MCIPWRAL=SD_PWR_IS_ACTIVE_LOW
System Control and Status
| EMCSC | EMC Shift Control. Controls how addresses are output on the EMC address pins for static memories. Also see Section 9.9 in the EMC chapter. 0 (STATIC_MEMORY_ADDRES): Static memory addresses are shifted to match the data bus width. For example, when accessing a 32-bit wide data bus, the address is shifted right 2 places such that bit 2 is the LSB. In this mode, address bit 0 for the this device is connected to address bit 0 of the memory device, thus simplifying memory connections. This also makes a larger memory address range possible, because additional upper address bits can appear on the higher address pins due to the shift. 1 (STATIC_MEMORY_ADDRES): Static memory addresses are always output as byte addresses regardless of the data bus width. For example, when word data is accessed on a 32-bit bus, address bits 1 and 0 will always be 0. In this mode, one or both lower address bits may not be connected to memories that are part of a bus that is wider than 8 bits. This mode matches the operation of LPC23xx and LPC24xx devices. |
| EMCRD | EMC Reset Disable[1]. External Memory Controller Reset Disable. Also see Section 9.8 in the EMC chapter. 0 (BOTH_EMC_RESETS_ARE_): Both EMC resets are asserted when any type of chip reset event occurs. In this mode, all registers and functions of the EMC are initialized upon any reset condition. 1 (MANY_PORTIONS_OF_THE): Many portions of the EMC are only reset by a power-on or brown-out event, in order to allow the EMC to retain its state through a warm reset (external reset or watchdog reset). If the EMC is configured correctly, auto-refresh can be maintained through a warm reset. |
| EMCBC | External Memory Controller burst control. Also see Section 9.10 in the EMC chapter. 0 (BURST_ENABLED_): Burst enabled. 1 (BURST_DISABLED_THIS): Burst disabled. This mode can be used to prevent multiple sequential accesses to memory mapped I/O devices connected to EMC static memory chip selects. These unrequested accesses can cause issues with some I/O devices. |
| MCIPWRAL | MCIPWR Active Level[1]. Selects the active level of the SD card interface signal SD_PWR. 0 (SD_PWR_IS_ACTIVE_LOW): SD_PWR is active low (inverted output of the SD Card interface block). 1 (SD_PWR_IS_ACTIVE_HIG): SD_PWR is active high (follows the output of the SD Card interface block). |
| OSCRS | Main oscillator range select. 0 (THE_FREQUENCY_RANGE_): The frequency range of the main oscillator is 1 MHz to 20 MHz. 1 (THE_FREQUENCY_RANGE_): The frequency range of the main oscillator is 15 MHz to 25 MHz. |
| OSCEN | Main oscillator enable. 0 (THE_MAIN_OSCILLATOR_): The main oscillator is disabled. 1 (THE_MAIN_OSCILLATOR_): The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins. |
| OSCSTAT | Main oscillator status. 0 (THE_MAIN_OSCILLATOR_): The main oscillator is not ready to be used as a clock source. 1 (THE_MAIN_OSCILLATOR_): The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |